Layout considerations.

This commit is contained in:
2025-02-20 02:18:31 -05:00
parent 01534db677
commit 6e8dc2e9db
5 changed files with 146466 additions and 141520 deletions

1
.gitignore vendored
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@@ -1 +1,2 @@
*-backups/
*.lck

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@@ -38,8 +38,8 @@
"other_text_upright": false,
"pads": {
"drill": 0.0,
"height": 4.2926,
"width": 1.8034
"height": 1.8,
"width": 1.325
},
"silk_line_width": 0.1,
"silk_text_italic": false,
@@ -48,7 +48,7 @@
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.25
"min_clearance": 0.35
}
},
"diff_pair_dimensions": [
@@ -209,9 +209,9 @@
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"min_amplitude": 0.1,
"single_sided": false,
"spacing": 0.6
"spacing": 0.1
}
},
"via_dimensions": [
@@ -485,6 +485,23 @@
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Display",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgb(242, 0, 11)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
@@ -492,7 +509,28 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "Display",
"pattern": "/Rpi CM4/R."
},
{
"netclass": "Display",
"pattern": "/Rpi CM4/G."
},
{
"netclass": "Display",
"pattern": "/Rpi CM4/B."
},
{
"netclass": "Display",
"pattern": "/Rpi CM4/.SYNC"
},
{
"netclass": "Display",
"pattern": "/Rpi CM4/DCLK"
}
]
},
"pcbnew": {
"last_paths": {
@@ -638,6 +676,14 @@
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"meta": {
"version": 0
},
"model_mode": 4,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,

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197654
fp-info-cache

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